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november 2010 doc id 14860 rev 4 1/43 1 STA680 hd radio? baseband receiver features iboc (in-band on-channel) digital audio broadcast signal decoding for am/fm hybrid and all-digital modes dual-channel hd 1.5 for background scanning and data services hd codec (hdc) audio decompression metadata support for hd radio reception mps (main program service) and pad (program associated data) data decoder advanced hd radio feature support: ? conditional access (ca) ? apple id3 tag ? multicasting ? electronic program guide (epg) ? real-time traffic ? audio time shifting variable input base-band data-rate i2s-like interface supporting 650, 675, 744.1875, 882, 912 ks/s data rates secondary rf base-band interface for dual tuner applications glueless interface to synchronous sdram addressing up to 512 mbit of sdram in x16 configuration optional serial flash memory spi interface for application code storage iis serial audio interface with programmable sample rate converter primary and secondary serial interfaces for based on industry standard iic and spi several general purpose ios one internal clock osc illator and two internal plls external clock input 1.2 v core supply; 3.3 v i/o supply automotive qualified in accordance with aec-q100 description the STA680 is an hd-radio base-band processor for car-radio applications. the STA680 functionality includes audio decompression and data processing, while multiple interfaces ensure flexible integration into the system. the STA680 takes full advantage of hd 1.5 radio benefits including cd-like audio quality from hd radio fm broadcasts and fm-like audio quality using hd radio am, while program associated data or traffic information is received from the second channel. lqfp144 (20x20x1.4 mm) lfbga 168 balls (12x12x1.4 mm) table 1. device summary order code package (1) 1. ecopack? compliant. packing STA680 lfbga 168 balls (12x12x1.4 mm) tray STA680q lqfp144 (20x20mm) tray www.st.com free datasheet http://www.datasheet-pdf.com/
contents STA680 2/43 doc id 14860 rev 4 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.1 lqfp description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.2 lfbga description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.3 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.4 i/os supply groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 receiver system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 hd radio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 dual channel hd 1.5 radio processing . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 overview of main functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.1 adjacent channel filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.2 hifi2 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.3 vectra core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.4 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.5 hardware accelerator (viterbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 operation and general remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 power supply ramp-up phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 oscillator setting time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 normal operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 digital i/o and memory interf aces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 interfaces: lqfp vs. lfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 base-band i 2 s interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 base-band i 2 s interface frequency diversity . . . . . . . . . . . . . . . . . . . . . . 27 5.4 audio interface (aif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 free datasheet http://www.datasheet-pdf.com/
STA680 contents doc id 14860 rev 4 3/43 5.4.1 output serial audio interface (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4.2 audio sample rate converter (asrc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 serial peripheral interfaces (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5.1 host micro serial peripheral interface (spi1) . . . . . . . . . . . . . . . . . . . . . 31 5.5.2 flash serial peripheral interface (spi2) . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.6 i 2 c interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6.1 host micro i 2 c interface (i2c1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 free datasheet http://www.datasheet-pdf.com/
list of tables STA680 4/43 doc id 14860 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. reference clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. power on timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. interface list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. baseband interfaces pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. bbi timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8. aif pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. serial audio interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10. spi interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. host micro spi pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 12. flash spi pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. host and auxiliary i 2 c interface pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. i 2 c interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. i2c1 interface device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. sdram interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. sdram interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 19. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 20. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 free datasheet http://www.datasheet-pdf.com/
STA680 list of figures doc id 14860 rev 4 5/43 list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. lqfp pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. lfbga ball-out (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. functional block diagram for hd radio demodulating and decoding . . . . . . . . . . . . . . . . . 18 figure 6. clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. power on timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. crystal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. bbi waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. serial audio interface waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11. spi interface timings diagrams and waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. timing diagrams and waveform for the two i 2 c interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 13. timing diagrams and waveform for the sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. lqfp144 (20x20mm) mechanical data and packa ge dimensions . . . . . . . . . . . . . . . . . . . 40 figure 15. lfbga 168 balls (12x12x1.4 mm) mechanical data and package dimensions . . . . . . . . . 41 free datasheet http://www.datasheet-pdf.com/
block diagram and pin description STA680 6/43 doc id 14860 rev 4 1 block diagram and pin description 1.1 block diagram figure 1. functional block diagram rf tuner (i.e. tda7706) rf tuner (i.e. tda7706) 8mb sdram 1mb serial flash (bootable) peripheral bus ahb bus STA680 i2s bbi 1 bbi 2 baseband interface audio interface crystal oscillator spi flash spi sd/mmc spi/i2c micr i/f main micro viterbi dma otp clock gen. unit ahb/apb bridge sdram interface core system vectra lx tensilica dsp hifi tensilica core boundary scan jtag system pll peripheral pll i/o & control interface ldo gpio xtal 28224 turner & audio interface free datasheet http://www.datasheet-pdf.com/
STA680 block diagram and pin description doc id 14860 rev 4 7/43 1.2 pin description the STA680 is available in two different packages targeting different application cost and complexity. it comes both in a 20x20mm lqfp package with 144 pins, and in a 12x12mm lfbga with 169 balls with 0.8mm pitch. 1.2.1 lqfp description figure 2 presents the pinout of the STA680 for the lqfp package option. different colors have been used for i/o signals from different interfaces according to ta b l e 2 reported in section 1.2.3 . figure 2. lqfp pinout (top view) vdd vdd gnd sdr_a3 sdr_a2 sdr_a1 sdr_a0 sdr_a10 gnd_ram_io vdd_ram_io sdr_ba1 sdr_ba0 sdr_cs_n gnd vdd sdr_ras sdr_cas sdr_we_n sdr_a4 gnd_ram_io vdd_ram_io sdr_a5 sdr_a6 sdr_a7 gnd vdd sdr_a8 sdr_a9 sdr_a11 sdr_a12 gnd_ram_io vdd_ram_io sdr_cke sdr_dqm1 sdr_dqm0 gnd sdr_d7 sdr_d6 sdr_d5 vdd_ram_io gnd_ram_io sdr_d4 sdr_d3 sdr_d2 vdd gnd sdr_d1 sdr_d0 sdr_d8 sdr_d9 vdd_ram_io gnd_ram_io sdr_d10 sdr_d11 sdr_d12 vdd gnd sdr_d13 sdr_d14 sdr_d15 sdr_feed_clk sdr_clk_ram3v3 gnd_ram_io_1v8 vdd_ram_io_1v8 gnd vdd spi2_ss1_n spi2_miso spi2_sck spi2_ss0_n spi2_mosi vdd_fsh_io gnd gnd_gen_io vdd_gen_io bb1_i bb1_ws bb1_bck spdif audio_in_abck audio_in_aws vdd gnd gnd_gen_io vdd_gen_io audio_in_adat dac256x adat3 adat2 adat aws abck clk_in gnd vdd gnd_pll_dig vdd_pll_dig gnd_pll0_ana vdd_pll0_ana gnd_osc vdd_osc osc_in osc_out vdd_reg3v3 vdd_reg1v8 gnd vdd gnd_fsh_io 144 143 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 108 2 107 3 106 4 105 5 104 6 103 7 102 8 101 9 100 10 99 11 98 12 97 13 96 14 95 15 94 16 93 17 92 18 91 19 90 20 89 21 88 22 87 23 86 24 85 25 84 26 83 27 82 28 81 29 80 30 79 31 78 32 77 33 76 34 75 35 74 36 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 142 testmode trst_n tck tms tdi tdo rts_gpio0 vdd gnd cts_gpio1 gnd_gen_io vdd_gen_io txd_gpio2 rxd_gpio3 reset_n spi1_ss0_n spi1_sck spi1_mosi vdd gnd spi1_miso gnd_gen_io vdd_gen_io iic1_scl iic1_sda bb2_q gnd vdd gnd_gen_io vdd_gen_io bb2_i bb2_ws bb2_bck blend bb1_q vdd ac00504 color legend: sdram interface jtag interface base band input interface flash interface host microprocessor interface uart gpio interface audio input interface audio output interface free datasheet http://www.datasheet-pdf.com/
block diagram and pin description STA680 8/43 doc id 14860 rev 4 1.2.2 lfbga description figure 3 presents the ball-out of the STA680 for the lfbga package option. different colors have been used for i/o signals from different interfaces according to ta b l e 2 reported in section 1.2.3 . figure 3. lfbga ball-out (top view) 1234567891011121314 a b c d e f g h j k l m n p gpio6 bb2_bck bb2_i gnd_gen_io iic1_sda spi1_miso spi1_sck reset_n txd_gpio2 rts_gpio0 vdd_gen_io testmode gpio5 bb1_q blend bb2_ws gnd_gen_io bb2_q iic1_scl spi1_mosi spi1_ss0_n rxd_gpio3 cts_gpio1 vdd_gen_io sdr_a3 sdr_a3 trst_n trst_n bb1_ws bb1_i adat2 iic2_sda gpio7 iic2_scl iic1_da spi3_mosi spi3_miso spi3_sck tdi tck sdr_a1 sdr_a1 sdr_a2 sdr_a2 vdd_gen_io vdd_gen_io bb1_bck iic2_da vdd vdd spi3_ss_n gpio4 tdo tms sdr_a10 sdr_a10 sdr_a0 sdr_a0 audio_in_ abck spdif adat3 vdd_pll_dig vdd modeop_fsh sdr_ba0 sdr_ba0 sdr_ba1 sdr_ba1 audio_in_ adat audio_in_ aws gnd_pll_ dig gnd_pll_ dig gnd gnd gnd gnd vdd modeop_gen sdr_ras_n sdr_ras_n sdr_cs_n sdr_cs_n aws adat dac256x gnd gnd gnd gnd sdr_cas_n sdr_cas_n sdr_we_n sdr_we_n vdd_ram_io vdd_ram_io gnd_gen_io gnd_gen_io abck gnd gnd gnd gnd sdr_a4 sdr_a4 sdr_a5 sdr_a5 gnd_ram_io gnd_ram_io vdd_osc gnd_osc gnd_pll1_ ana gnd_pll0_ ana gnd gnd gnd gnd vdd vdd sdr_a7 sdr_a7 sdr_a6 sdr_a6 osc_out clk_in vdd vdd_reg3v3 vdd vdd sdr_a9 sdr_a9 sdr_a8 sdr_a8 osc_in gnd_osc vdd vdd_reg3v3 vdd_fsh_io gnd_fsh_io vdd_ram_io _1v8 gnd_ram_io _1v8 gnd_ram_io gnd_ram_io sdr_a12 sdr_a12 sdr_a11 sdr_a11 vdd_pll1_ ana vdd_pll0_ ana spi2_ss1_n spi2_ss2_n spi2_ss3_n rfu sdr_d13 sdr_d10 vdd_ram_io vdd_ram_io gnd_ram_io gnd_ram_io sdr_dqm1 sdr_cke vdd_reg1v8 vdd_reg1v8 spi2_mosi spi2_sck sdr_clk_ ram3v3 sdr_d15 sdr_d15 sdr_d12 sdr_d12 sdr_d9 sdr_d9 sdr_d0 sdr_d0 sdr_d2 sdr_d2 sdr_d4 sdr_d4 sdr_d6 sdr_d6 sdr_dqm0 spi2_ss0_n spi2_miso sdr_feed_ clk sdr_d14 sdr_d14 sdr_d11 sdr_d11 sdr_d8 sdr_d8 sdr_d1 sdr_d1 sdr_d3 sdr_d3 sdr_d5 sdr_d5 sdr_d7 sdr_d7 ball unused ball not present ac0070 7 color legend: sdram interface base band input interface flash interface host micro- processor interface uart gpio interface audio input interface audio output interface jtag interface memory card interface free datasheet http://www.datasheet-pdf.com/
STA680 block diagram and pin description doc id 14860 rev 4 9/43 1.2.3 pin list the ta bl e 2 describes the primary function and behavior of the STA680 pins. table 2. pins description pin # ball # signal name type pull-up /down (1) electrical supply group description test 1 a13 testmode i pull-down 1.8 v or 3.3 v generic io supply factory test mode enable standard 1149.1 jtag interface 2 b14 trst_n i pull-up 1.8 v or 3.3 v generic io supply jtag active-low test reset 3 c12 tck i pull-down 1.8 v or 3.3 v generic io supply jtag test clock 4 d12 tms i pull-up 1.8 v or 3.3 v generic io supply jtag test mode state 5 c11 tdi i pull-up 1.8 v or 3.3 v generic io supply jtag test data in 6 d11 tdo o - 1.8 v or 3.3 v generic io supply jtag test data out gpio & uart interfaces 7a11 rts_gpio0 i/o pull-up 1.8 v or 3.3 v generic io supply uart ready to send / gpio bit 0 10 b11 cts_gpio1 i/o pull-up 1.8 v or 3.3 v generic io supply uart clear to send / gpio bit 1 13 a10 txd_gpio2 i/o pull-up 1.8 v or 3.3 v generic io supply uart transmit data / gpio bit 2 14 b10 rxd_gpio3 i/o pull-up 1.8 v or 3.3 v generic io supply uart receive data / gpio bit 3 not bonded d10 gpio4 i/o pull-up 1.8 v or 3.3 v generic io supply gpio bit 4 not bonded b1 gpio5 i/o pull-up 1.8 v or 3.3 v generic io supply gpio bit 5 not bonded a2 gpio6 i/o pull-up 1.8 v or 3.3 v generic io supply gpio bit 6 not bonded c5 gpio7 i/o pull-up 1.8 v or 3.3 v generic io supply gpio bit 7 reset 15 a9 reset_n i pull-up 1.8 v or 3.3 v generic io supply device active-low reset free datasheet http://www.datasheet-pdf.com/
block diagram and pin description STA680 10/43 doc id 14860 rev 4 host processor interfaces 16 b9 spi1_ss0_n i pull-up 1.8 v or 3.3 v generic io supply spi interface 1 active-low slave select 17 a8 spi1_sck i pull-up 1.8 v or 3.3 v generic io supply spi interface 1 serial clock 18 b8 spi1_mosi i pull-up 1.8 v or 3.3 v generic io supply spi interface 1 serial data master out/slave in 21 a7 spi1_miso o pull-up 1.8 v or 3.3 v generic io supply spi interface 1 serial data master in/slave out 24 b7 iic1_scl i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 1 serial clock line 25 a6 iic1_sda i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 1 serial data line not bonded c7 iic1_da i/o pull-up 1.8 v or 3.3 v generic io supply iic interface 1 data acknowledged not bonded c6 iic2_scl i/o pull-up 1.8 v or 3.3 v generic io supply reserved not bonded c4 iic2_sda i/o pull-up 1.8 v or 3.3 v generic io supply reserved not bonded d4 iic2_da i/o pull-up 1.8 v or 3.3 v generic io supply reserved iis tuner interfaces 40 c2 bb1_i i pull-down 1.8 v or 3.3 v generic io supply primary baseband interface serial i data 35 b2 bb1_q i pull-down 1.8 v or 3.3 v generic io supply primary baseband interface serial q data 41 c1 bb1_ws i pull-down 1.8 v or 3.3 v generic io supply primary baseband interface word strobe 42 d3 bb1_bck i pull-down 1.8 v or 3.3 v generic io supply primary baseband interface bit clock 31 a4 bb2_i i pull-down 1.8 v or 3.3 v generic io supply secondary baseband interface serial i data 26 b6 bb2_q i pull-down 1.8 v or 3.3 v generic io supply secondary baseband interface serial q data 32 b4 bb2_ws i pull-down 1.8 v or 3.3 v generic io supply secondary baseband interface word strobe 33 a3 bb2_bck i pull-down 1.8 v or 3.3 v generic io supply secondary baseband interface bit clock table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description free datasheet http://www.datasheet-pdf.com/
STA680 block diagram and pin description doc id 14860 rev 4 11/43 iis audio input interface 45 f2 audio_in_aws i pull-up 1.8 v or 3.3 v generic io supply reserved 44 e1 audio_in_abck i pull-up 1.8 v or 3.3 v generic io supply reserved 50 f1 audio_in_adat i pull-down 1.8 v or 3.3 v generic io supply reserved audio output interfaces 55 g1 aws i/o pull-up 1.8 v or 3.3 v generic io supply digital audio output word strobe 56 h3 abck i/o pull-up 1.8 v or 3.3 v generic io supply digital audio output clock 54 g2 adat o - 1.8 v or 3.3 v generic io supply digital audio output serial data 53 c3 adat2 o - 1.8 v or 3.3 v generic io supply reserved 52 e3 adat3 o - 1.8 v or 3.3 v generic io supply reserved 43 e2 spdif o - 1.8 v or 3.3 v generic io supply reserved 34 b3 blend o - 1.8 v or 3.3 v generic io supply digital audio output blend output 51 g3 dac256x o - 1.8 v or 3.3 v generic io supply digital audio output oversampling clock clock & oscillator 57 k2 clk_in i - 1.8 v or 3.3 v generic io supply reference digital clock 66 l1 osc_in ana - 1.8 v osc supply 28,224mhz crystal in or digital clock input 67 k1 osc_out ana - 1.8 v osc supply crystal output spi flash interface 78 p4 spi2_miso i pull-up 1.8 v or 3.3 v flash io supply spi interface 2 serial data master in/slave out 74 n3 spi2_mosi o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 serial data master out/slave in 75 p3 spi2_ss0_n o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 active-low slave select 0 77 m3 spi2_ss1_n o pull-up 1.8 v or 3.3 v flash io supply reserved not bonded m4 spi2_ss2_n o pull-up 1.8 v or 3.3 v flash io supply reserved table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description free datasheet http://www.datasheet-pdf.com/
block diagram and pin description STA680 12/43 doc id 14860 rev 4 not bonded m5 spi2_ss3_n o pull-up 1.8 v or 3.3 v flash io supply reserved 76 n4 spi2_sck o pull-up 1.8 v or 3.3 v flash io supply spi interface 2 serial clock spi sd/mmc interface not bonded c9 spi3_miso i pull-up 1.8 v or 3.3 v generic io supply reserved not bonded c8 spi3_mosi o pull-up 1.8 v or 3.3 v generic io supply reserved not bonded d9 spi3_ss_n o pull-up 1.8 v or 3.3 v generic io supply reserved not bonded c10 spi3_sck o pull-up 1.8 v or 3.3 v generic io supply reserved sdram interface 84 p5 sdr_feed_clk i - 3.3 v sdram io supply feedback clock from sdram interface 83 n5 sdr_clk_ram 3v3 o - 3.3 v sdram io supply clock to sdram for 3.3 v interface 97 n9 sdr_d0 i/o - 3.3 v sdram io supply sdram bidirectional data bit 0 98 p9 sdr_d1 i/o - 3.3 v sdram io supply sdram bidirectional data bit 1 101 n10 sdr_d2 i/o - 3.3 v sdram io supply sdram bidirectional data bit 2 102 p10 sdr_d3 i/o - 3.3 v sdram io supply sdram bidirectional data bit 3 103 n11 sdr_d4 i/o - 3.3 v sdram io supply sdram bidirectional data bit 4 106 p11 sdr_d5 i/o - 3.3 v sdram io supply sdram bidirectional data bit 5 107 n12 sdr_d6 i/o - 3.3 v sdram io supply sdram bidirectional data bit 6 108 p12 sdr_d7 i/o - 3.3 v sdram io supply sdram bidirectional data bit 7 96 p8 sdr_d8 i/o - 3.3 v sdram io supply sdram bidirectional data bit 8 95 n8 sdr_d9 i/o - 3.3 v sdram io supply sdram bidirectional data bit 9 92 m8 sdr_d10 i/o - 3.3 v sdram io supply sdram bidirectional data bit 10 91 p7 sdr_d11 i/o - 3.3 v sdram io supply sdram bidirectional data bit 11 table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description free datasheet http://www.datasheet-pdf.com/
STA680 block diagram and pin description doc id 14860 rev 4 13/43 90 n7 sdr_d12 i/o - 3.3 v sdram io supply sdram bidirectional data bit 12 87 m7 sdr_d13 i/o - 3.3 v sdram io supply sdram bidirectional data bit 13 86 p6 sdr_d14 i/o - 3.3 v sdram io supply sdram bidirectional data bit 14 85 n6 sdr_d15 i/o - 3.3 v sdram io supply sdram bidirectional data bit 15 111 n13 sdr_dqm0 o - 3.3 v sdram io supply low-byte data input/output mask 112 m13 sdr_dqm1 o - 3.3 v sdram io supply high-byte data input/output mask 128 g13 sdr_we_n o - 3.3 v sdram io supply active-low write enable 129 g12 sdr_cas_n o - 3.3 v sdram io supply active-low column address strobe 130 f13 sdr_ras_n o - 3.3 v sdram io supply active-low row address strobe 113 m14 sdr_cke o - 3.3 v sdram io supply clock enable 133 f14 sdr_cs_n o - 3.3 v sdram io supply active-low chip select 134 e13 sdr_ba0 o - 3.3 v sdram io supply bank select address 0 135 e14 sdr_ba1 o - 3.3 v sdram io supply bank select address 1 139 d14 sdr_a0 o - 3.3 v sdram io supply address bit 0 to sdram 140 c13 sdr_a1 o - 3.3 v sdram io supply address bit 1 to sdram 141 c14 sdr_a2 o - 3.3 v sdram io supply address bit 2 to sdram 142 b13 sdr_a3 o - 3.3 v sdram io supply address bit 3 to sdram 127 h12 sdr_a4 o - 3.3 v sdram io supply address bit 4 to sdram 124 h13 sdr_a5 o - 3.3 v sdram io supply address bit 5 to sdram 123 j14 sdr_a6 o - 3.3 v sdram io supply address bit 6 to sdram 122 j13 sdr_a7 o - 3.3 v sdram io supply address bit 7 to sdram table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description free datasheet http://www.datasheet-pdf.com/
block diagram and pin description STA680 14/43 doc id 14860 rev 4 119 k14 sdr_a8 o - 3.3 v sdram io supply address bit 8 to sdram 118 k13 sdr_a9 o - 3.3 v sdram io supply address bit 10 to sdram 138 d13 sdr_a10 o - 3.3 v sdram io supply address bit 10 to sdram 117 l14 sdr_a11 o - 3.3 v sdram io supply address bit 11 to sdram 116 l13 sdr_a12 o - 3.3 v sdram io supply address bit 12 to sdram supplies not bonded f12 modeop_gen i pull-up 3.3 v sdram io supply define the opereting voltage of the "generic i/o" supply group. if tied low the i/os work at 1.8v else they work at 3.3v. default value is 3.3v. not bonded e12 modeop_fsh i pull-up 3.3 v sdram io supply define the opereting voltage of the "flash i/o" supply group. if tied low the i/os work at 1.8v else they work at 3.3v. default value is 3.3v. 8, 19, 28, 36, 46, 59, 71, 79, 89, 100, 109, 120, 131, 144 d5, d6, e11, f11, j11, j12, k3, k11, k12, l3 vdd n/a - 1.2 v core supply p ower supply for core logic 9, 20, 27, 37, 47, 58, 70, 80, 88, 99, 110, 121, 132, 143 f6, f7, f8, f9, g6, g7, g8, g9, h6, h7, h8, h9, j6, j7, j8, j9 gnd n/a - - core supply ground for core logic table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description free datasheet http://www.datasheet-pdf.com/
STA680 block diagram and pin description doc id 14860 rev 4 15/43 11, 22, 29, 38, 48 a5, b5, h1, h2 gnd _gen_io n/a - - generic io supply generic i/os ground 12, 23, 30, 39, 49 a12, b12, d1, d2 vdd_gen_io n/a - 1.8 v or 3.3 v generic io supply generic i/os p ower supply 72 l6 gnd _fsh_io n/a - - flash io supply g round for flash interface i/os 73 l5 vdd_fsh_io n/a - 1.8 v or 3.3 v flash io supply p ower supply for flash inteface i/os 93, 104, 115, 126, 137 h14, l11, l12, m11, m12 gnd_ram_io n/a - - sdram io supply g round for sdram interface i/os 94, 105, 114, 125, 136 g14, m9, m10 vdd_ram_io n/a - 3.3 v sdram io supply p ower supply for sdram interface i/os 60 f3, f4 gnd_pll_dig n/a - - pll digital supply g round for pll digital part 61 e4 vdd_pll_dig n/a - 1.2 v pll digital supply p ower supply for pll digital part 62 j4 gnd_pll0_ana n/a - - pll analog supply g round for pll0 analog part (2) 62 j3 gnd_pll1_ana n/a - - pll analog supply g round for pll1 analog part (2) 63 m2 vdd_pll0_ana n/a - 1.8 v pll analog supply p ower supply for pll0 analog part (3) 63 m1 vdd_pll1_ana n/a - 1.8 v pll analog supply p ower supply for pll1 analog part (3) 64 j2, l2 gnd_osc n/a - - osc supply g round for oscillator core 65 j1 vdd_osc n/a - 1.8 v osc supply p ower supply for oscillator core 68 k4, l4 vdd_reg3v3 n/a - 3.3 v ldo supply voltage regulator input power supply@ 3.3 volt 69 n1, n2 vdd_reg1v8 n/a - 1.8 v ldo supply voltage regulator output power supply@1.8 volt table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description free datasheet http://www.datasheet-pdf.com/
block diagram and pin description STA680 16/43 doc id 14860 rev 4 1.2.4 i/os supply groups the STA680 i/o signals can be grouped into three different supply domains, as shown in (see ta b l e 2 ): generic io supply flash io supply sdram io supply group in the lqfp package option all three groups must be supplied with 3.3 v. in the lfbga package the three supply groups can independently operate at 3.3 v or 1.8 v. the sdram_io supply group must always be supplied with 3.3 v. the modeop_gen pin selects the operating voltage of the generic_io supply group. if it is shorted to ground then all the i/o signals belonging to the generic_io supply group will work at 1.8 v; if the modeop_gen pin is left floating or is tied to 3.3 v all the group i/os will operate at 3.3 v. the modeop_fsh pin selects the operating voltage of the flash_io supply group. if it is shorted to ground then all the i/o sign als belonging to the flash_io supply group will work at 1.8 v; if the modeop_fsh pin is left floating or is tied to 3.3 v the flash interface i/os will operate at 3.3 v. 82 l9 vdd_ram_io _1v8 n/a - 1.8 v n/a reserved - connect to 1.8 v supplyt 81 l10 gnd_ram_io _1v8 n/a - - n/a reserved - connect to ground others not bonded m6 rfu n/a - n/a n/a reserved for future use - do not connect 1. each input pin has a pull-up/down resistor to its default value. unless otherwise specified, unused pins can be left unconnected after verifying that the impedance value of the pull-up/down resistor (see table 20 ) is sufficient to guarantee noise immunity in user application environment. 2. in the lqfp package gnd_pll0_ana and gnd_pll1_ana are bonded together. 3. in the lqfp package vdd_pll0_ana and vdd_pll1_ana are bonded together. table 2. pins description (continued) pin # ball # signal name type pull-up /down (1) electrical supply group description free datasheet http://www.datasheet-pdf.com/
STA680 general description doc id 14860 rev 4 17/43 2 general description the STA680 is a system-on-chip designed for demodulating and decoding hd radio signals. the STA680 is the base-band signal processor needed by an hd radio receiver: it includes the ofdm demodulator and error correction and the audio and data decoding of the digital channel. figure 4. system block diagram the architecture of STA680 consists of a mixed hardware/software implementation. computation-intensive functional blocks are implemented using custom logic. software implementation is more efficient for functi onal blocks where flexibility is needed. 2.1 receiver system overview such flexibility enables the STA680 to support both the hd 1.0 single-channel, and hd 1.5 double-channel applications, as shown in figure 5 shows the internal simplified block diagram of the STA680. the STA680 receives the digital base-band signal from the digital tuner (e.g. tda7706) and extracts the hd-encoded audio and data services as shown in figure 5 . STA680 is compatible with conventional base-band radio reception tuners (e.g. tda7706). sta 680 tda7706 bb_clk bb_ wcl k bb _i bb _q i2s _clk i2s_wclk i2s _d digital audio base -band i2s interface optional audio processing blended l/r ble nd fm/am fm/am dac bb_clk bb_ wclk bb _i bb _q serial nor- flash memory micro- processor sdram i2c/spi spi 2 tda7706 free datasheet http://www.datasheet-pdf.com/
general description STA680 18/43 doc id 14860 rev 4 figure 5. functional block diagram for hd radio demodulating and decoding 2.2 hd radio processing the STA680 hd radio decoder performs the processing of the iboc signal. the native internal processing data rate is 744.1875 ks/s for fm and 46.51171875 ks/s for am. the input i 2 s base-band interface accepts several input sample rates thanks to the availability of a re configurable sample rate converter.th e supported rates are: 650 ks/s, 675 ks/s, 882 ks/s and 912 ks/s. the STA680 is responsible for the detection, acquisition and demodulation of the iboc signal. this processing is mainly performed inside the vectra dsp core. the demodulated signal is then passed to the hi-fi processor for decoding and handling of data services. the digital 44.1 khz decompressed audio is streamed out by means of the digital audio interface. the STA680 requires a 4mwords x16bits external sdram (with up to 32mword x16bits supported) for data storage in order to process the hd radio stream 2.3 dual channel hd 1.5 radio processing the is capable of simultaneously demodulating two different hd radio streams. this feature enables the device to decode the main hd radio audio stream in parallel with the data service broadcast by a different radio channel (for instance this feature allows to continue receiving traffic information provided by one radio station while listing to music from a different station). the implementation of the dual stream hd radio processing requires that two am/fm rf tuners be connected to the STA680, as shown in figure 4 src main bb src src secondary bb src ofdm demod psk/qam demod deinterleaver and convolutional decoding channel decoder ofdm demod psk/qam demod deinterleaver and convolutional decoding channel decoder digital demux hdc decoder data processing source decoder blending logic blending signal sample rate converter and serial interfaces data i2s spi i2c bbi1 bbi2 free datasheet http://www.datasheet-pdf.com/
STA680 general description doc id 14860 rev 4 19/43 2.4 overview of main functional blocks 2.4.1 adjacent channel filter this module performs digital filtering of the iboc channel. it receives the complex base- band i/q iboc signal input from the tuner and pre-conditions the signal for subsequent modem processing. 2.4.2 hifi2 core the hifi2 is a signal processing engine specif ically designed to provide high quality 24-bit audio processing. the hifi2 uses the tensilica xtensa lx engine wit h additional useful hardware capab ilities such as: specialized instructions for 24-bit audio mac & stream coding dual mac (each supports 24 x 24 and 32 x 16 bit format) huffman encode / decode and truncate functions two way single-instruction-multiple-data arithmetic and logic operations 2.4.3 vectra core the vectra lx is a powerful, configurable 32-bit risc engine optimized for dsp with vliw capabilities. the vectra lx on board the STA680 includes eight mac units, sixteen 160-bit vector operation registers, and a number of simd arithmetic instructions. custom instructions in the vectra are tailored to d sp applications such as filters and ffts. the vectra processor has been further configured with specific instructions for efficient performance on the hd radio application. 2.4.4 dma a ten-channel dma controller is attached to the ahb bus to allow the vectra and hifi2 processor cores to efficiently move large data-blocks. 2.4.5 hardware accelerator (viterbi) the complex convolutional viterbi hardware accelerator supports both k constant of 7 and 9, for iboc digital fm and am processing respectively. free datasheet http://www.datasheet-pdf.com/
operation and general remarks STA680 20/43 doc id 14860 rev 4 3 operation and general remarks 3.1 clock schemes the STA680 needs an external clock source to drive the internal phase locked loops (plls) that generates the clocks needed by the dsp cores and its peripherals. the STA680 accepts several external reference clock sources, as listed below: the reference clock can be supplied through the use of an external crystal or as a digital signal coming from an external ic. the reference clock can have different frequencies and can be fed to the STA680 through different input pins. the selection of the clock input mode is performed during the power-on phase of the device by latching the value of the pins adat3, blend and dac256x on the rising edge of the reset_n signal (see chapter 3.2 ); this value shall be selected according to ta b l e 3 . table 3. reference clock configuration [adat3, blend, dac256x] clock type input pin clock frequency (mhz) [0,0,0] (1) 1. default setting. crystal osc_in 28.224 [0,0,1] digital osc_in or clk_in (2) 2. when using osc_in pin to input the reference cloc k the clk_in pin must be connected to ground and vice versa. 23.3472 [0,1,0] digital osc_in or clk_in (2) 36.48 [0,1,1] digital osc_in or clk_in (2) 2.9184 [1,0,0] digital bb1_bck 10.4 [1,0,1] digital bb1_bck 10.8 [1,1,0] digital bb1_bck 14.112 [1,1,1] digital audio_in_abck 2.9184 free datasheet http://www.datasheet-pdf.com/
STA680 operation and general remarks doc id 14860 rev 4 21/43 figure 6 shows a simplified version of the internal clock generation unit. figure 6. clock generation unit clock generation unit some remarks on the clock input pin follows: osc_in is always a 1.8 v input pin. clk_in, bb1_bck and audio_in_abck are 3.3 v for the lqfp package, whereas they can be configured as either 3.3 v or 1.8 v pins for the lfbga (see chapter 1.2.4 ) when the clock is fed through the clk_in pin, the osc_in pin must be connected to ground. the bb1_bck pin is the bit clock of the digital interface to the baseband tuner. when this pin is selected as input for the reference clock, the selected clock frequency must be chosen compatibly with the primary baseband interface settings (see chapter 5.2 ): ? 10.4 mhz = 16 * 2 * 650 khz bbi set to 650 ksample/s ? 10.8 mhz = 16 * 2 * 675 khz bbi set to 675 ksample/s ? 14.112 mhz = 16 * 2 * 882 khz bbi set to 882 ksample/s the audio_in_abck pin is the bit clock of the digital audio input interface to the tuner. when this pin is selected as the refe rence lock source, the STA680 input serial audio interface must be configured as follows: ?slave mode ? input sample rate = 45.6 khz ? word length = 32 bit with this settings the reference clock freq uency is 2.9184 mhz = 32 * 2 * 45.6 khz. internal oscillator bb1_bck audio_in_abck clk_in osc_in osc_out adat3 blend dac256x encoder 2 osc_en clk_sel core clock pll peripheral clock pll pll settings clock to cores up to 166mhz clock to sdram up to 136 mhz (core in normal drive supply) up to 160 mhz (core in over drive supply) div2 sw application-controlled full - half frequency with 50% duty cycle clock to peripherals up to 70.56mhz (integer multiple of 44.1khz audio sampling rate) free datasheet http://www.datasheet-pdf.com/
operation and general remarks STA680 22/43 doc id 14860 rev 4 3.2 power on this chapter describes the power-on procedure fo r the cold start (i.e. when the device is not supplied before being turned on). figure 7 and ta bl e 4 show the timing for the power up sequence of the cold start. boot pins are latched at startup. their default value is logic 0, in case logic 1 is needed a 6k2 pull-up resistor is needed on the corresponding boot line. after reset release, the boot selection lines becomes outputs. figure 7. power on timing figure 8. crystal characteristics table 4. power on timing parameters symbol parameter min max unit t ramp-up external supply ramp-up time same ramp-up time for 3.3 v and 1.2 v supply - t dc1v8 dc1v8 regulator start-up time - 1 ms t osc (1) 1. the oscillator start-up time depends on the crystal connected to the intern al oscillator. the given value is estimated for a crystal with characteristic shown in figure 8 . oscillator start-up time - 400 s t rst reset release time 2 - ms t cfg,s setup time for clock configuration 0.1 - s t cfg,h hold time for clock configuration 10 - ns supply 1v2 supply 1v2 supply 3v3 t dc1v 8 supply 1v8 osc_in t osc_out reset_n t osc t rst adat3 blend dac256x clock configuration default (no drive on lines) -> crystal 28.22mhz selected as clock source t cfg,s t cfg,h high impedance stable data don?t care generated clocks primary boot min @ 2. 9184mhz max @ 38.48mhz secondary boot @ 28. 224mhz functional mode @ 127mhz model value rm 50 ohm lm 1.33 mh cm 26 ff co 7 pf ci = ci1 = ci3 38pf (33pf + 5pf parasitic) ci1 ci2 cm co rm lm equivalent circuit of a quartz crystal free datasheet http://www.datasheet-pdf.com/
STA680 power supply ramp-up phase doc id 14860 rev 4 23/43 4 power supply ramp-up phase the external power supply circuit on the board has to ensure that all the power supplies be ramped-up to their specified levels within the time t ramp-up , the ramp up phase of each power domain should start at the same time. the reset_n pin must be kept low since the beginning. for normal applications, the testmode pin (factory test mode enable, see ta bl e 3 ) must be connected to ground. 4.1 oscillator setting time once the power supply has reached the operating level, the internal voltage regulator gets functional after t dc1v8 = 1 s (see ta bl e 4 ) and starts supplying the 1.8 v voltage to internal ips such as plls and crystal oscillator. the pll is powered up but not yet functioning since the internal logic keeps it in bypass mode until a stable clock is available and STA680 has entered the secondary boot phase. as shown in figure 7 , if an external crystal is connected to the internal oscillator this will output a correct waveform after t osc = 400 s (see ta bl e 4 ). alternatively, if no crystal is used, a digital clock must be supplied according to the instructions detailed in section 3.1 . the reset_n pin must be kept low for an additional t rst = 1.1 s both when using a crystal and when using an external reference clock. as described in section 3.1 the internal clock configuration is defined by the status of the pins adat3, blend and dac256x; this is latched on the rising edge of the reset_n signal. the voltage of the three pins must be stable from at least t cfg = 0.1 s before the rising edge of the reset_n signal. 4.2 boot sequence once the reset_n signal has been released and the power up sequence correctly executed, the STA680 enters the boot proc edure, which consis ts of two phases: 1. device setup 2. application authentication and download. during the first phase, the STA680 executes the on-chip primary boot code contained in the boot rom. the primary boot synchronizes the internal cores, initializes the spi and iic interfaces and automatically selects the secondary boot code source by looking for a pre-defined pattern into uart1, flash, spi1, iic1 and iic2. once the source of the secondary boot code has been identified, the STA680 executes the following steps: 1. code authentication 2. sdram initialization 3. secondary boot code download to sdram. free datasheet http://www.datasheet-pdf.com/
power supply ramp-up phase STA680 24/43 doc id 14860 rev 4 in order to decrease the boot time during the secondary phase, the STA680 performs the setup of the plls and sets the internal clock frequency to 28.224 mhz (see figure 7 ). subsequently it downloads and validates the application code either from the external flash memory or from the host microcontroller. this ends the boot procedure. 4.3 normal operation mode after the execution of the boot code, the device enters the normal operation mode by jumping to the ma in program loop. free datasheet http://www.datasheet-pdf.com/
STA680 digital i/o and memory interfaces doc id 14860 rev 4 25/43 5 digital i/o and memory interfaces 5.1 interfaces: lqfp vs. lfbga the STA680 connectivity depends on the selected package. the differences between the two package options are listed in ta b l e 5 . table 5. interface list interface name direction lqfp lfbga baseband interface 1 i ?? baseband interface 2 (data only) i ?? i 2 s audio input i ?? i 2 s audio output (six channels) o ?? i 2 c primary interface (micro) i/o ?? i 2 c secondary interface i/o x ? spi micro interface i/o ?? spi flash interface (double chip select) i/o ?? spi flash interface extension (up to 4 chip select) i/o x ? spi sd/mmc i/o x ? sdram interface i/o ?? s/pdif interface o ?? uart interface i/o ?? 4 gpio lines i/o x ? jtag test interface (boundary scan only) i/o ?? free datasheet http://www.datasheet-pdf.com/
digital i/o and memory interfaces STA680 26/43 doc id 14860 rev 4 5.2 base-band i 2 s interface the STA680 has two digital base-band interfaces (bbi1 and bbi2), the tuners receive the analog signals from the antenna, sample them, perform down conversion and channel selection, and transmit the digital base-band streams to the STA680 by means of bbi1 and bbi2 each bb interface consists of four wires: two se rial data lines (i/q), one bit clock line and one frame clock line. the serial data is alwa ys transmitted with the msb first and a 16-bit word length. the complex base-band signal needs to be at zero if. most common data rates are supported by using the internal base-band sample rate converter. the allowed base-band interface data rates are: 650 ks/s, 675 ks/s, 882 ks/s 912 ks/s. ta bl e 6 . describes the pin functionality of both bbi1 and bbi2. the base-band interface supports the modes shown in figure 9 timing information for the protocols shown in figure 9 is detailed in in ta bl e 7 . table 6. baseband interfaces pin list pin name designation type drive bb1_ws secondary base band interface word strobe i - bb1_bck primary baseband interface bit clock i - bb1_i primary baseband interface serial i data i - bb1_q primary baseband interface serial q data i - bb2_ws secondary baseband interface word strobe i - bb2_bck secondary baseband interface bit clock i - bb2_i secondary baseband interface serial i data i - bb2_q secondary baseband interface serial q data i - free datasheet http://www.datasheet-pdf.com/
STA680 digital i/o and memory interfaces doc id 14860 rev 4 27/43 figure 9. bbi waveforms and timings 5.3 base-band i 2 s interface frequency diversity when the STA680 is paired with the tda7706 tuner it can benefit from the supported base- band interface frequency diversity that allows to improve the emi robustness of the system. the frequency diversity technique allows the base-band data-rate to be varied in run-time depending on the frequency of the tuned station, thus moving the intrinsic radiation of the bbi digital lines away from the signal of interest. i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 i15 i14 i13 i12 i11 ? ? i4 i3 i2 i1 i0 i15 i14 i13 i12 i11 ?? i4 i3 i2 i1 i0 q15 q14 q13 q12 q11 ... ... q4 q3 q2 q1 q0 q15 q14 q13 q12 q11 ? ? q4 q3 q2 q1 q0 sample n (i and q) sample n+1 (i and q) split mode bbx_ws bbx_bck bbx_i bbx_q sample n (i) sample n (q) sample n (i) sample n (q) bbx_ws bbx_bck bbx_i multiplexed mode i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 q15 q14 q13 q12 q11 ? ? q4 q3 q2 q1 q0 sample n (i) sample n (q) bbx_ws bbx_bck bbx_i afe mode ts th th ts th ts 2/fws 1/fws 1/fws 1/fbck,mux 1/fbck,split 1/fbck,afe ac00713 table 7. bbi timing values symbol parameter working rate unit min. max. fws word strobe 650 675 744.188 882 912 khz fbck, split bit clock in split mode 16 x fws - - - 66 mhz fbck, mux bit clock in mux mode 32 x fws - - - 32 x fws mhz fbck, afe bit clock in afe mode 32 x fws - - - 66 mhz th data hold time 4 - - - - ns ts data setup time 8 - - - - ns free datasheet http://www.datasheet-pdf.com/
digital i/o and memory interfaces STA680 28/43 doc id 14860 rev 4 5.4 audio interface (aif) the STA680 uses a stereo i 2 s interface for sending the decoded digital audio back to the tuner, where the blending with the legacy am/fm demodulated audio occurs. the receivers and transmitters can be used either in master mode, running with the STA680 internal audio frequency of 44.1 khz or in slave mode running with a frequency determined by the external device. in slave mode, the internal audio sample rate converter ((asrc, see chapter 5.4.2 ) adapts the external data rate (from 44.1 to 48 ksps) to the internal one. 5.4.1 output serial audio interface (sai) the output serial audio interface is used to send the decoded audio from the hd radio decoder to an external ic (e.g. tda7706). the output sai is an i2s interface which provides audio samples in stereo at a 44,1 ks/s data rate in master mode. in slave mode, other sample rates (from 44.1 to 48ksps) are supported by means of the internal asrc (see chapter 5.4.2 ). the output sai interface is composed by three lines: one data line and two clock lines. the output sai supports a 32x or 64x bit cl ock with 16-bit precision audio data. the 32x clock mode has not bit padding. the 64x clock mode adds 16-bits zero padding at the end of the 16-bit audio data. figure 10 shows timing diagrams for the supported modes. an oversampled audio master-clock is also available for directly interfacing the STA680 to an external dac. ta bl e 8 shows the timing values for the output sai interface. table 8. aif pin list pin name designation type drive aws digital audio output word strobe i/o 4ma abck digital audio output clock i/o 4ma adat digital audio output serial data o 4ma dac256x digital audio output oversampling clock (256 x fs) o 4ma blend digital audio output blend output o 4ma free datasheet http://www.datasheet-pdf.com/
STA680 digital i/o and memory interfaces doc id 14860 rev 4 29/43 figure 10. serial audio interface waveforms and timings 5.4.2 audio sample ra te converter (asrc) the STA680 embeds a stereo channel sample rate converter to be used in combination with either the output (one single data-line) or the input sai. the asrc has a total harmonic distortion plus noise (thd+n) level at 1 khz smaller than -85 db (0.0056%). the supported data rates are: 44,100 ( 10 hz), 45,600 ( 15 hz) 48,000 ( 15 hz) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 left right aws abck adat 32x mode (16 - bit data) d15 d14 d13 ? ? d3 d2 d1 d0 0 0 0 0 0d15 d14 d13 d3 d2 d1 d0 00 0 0 0 left right aws abck adat 64x mode (32 - bit data) ? ? 1/faws 1/faws 1/fabck,16 1/fabck,32 th ts ac00717 table 9. serial audio interface timing values symbol parameter working rate unit faws word strobe 44.1 10 hz 45.6 15 hz 48 15 hz khz fabck,16 bit clock for 16-bit data 32 x faws mhz fabck,32 bit clock for 32-bit data 64 x faws mhz th data hold time 5 ns ts data setup time 20 ns free datasheet http://www.datasheet-pdf.com/
digital i/o and memory interfaces STA680 30/43 doc id 14860 rev 4 5.5 serial peripheral interfaces (spi) the STA680 provides two serial peripheral interfaces: spi1 is intended for communicating with the host microcontroller. spi2 interfaces the STA680 to the external flash memory the maximum spi clock frequency in master mode is 25 mhz. in slave mode the maximum input clock frequency is a function of the internal peripheral clock. in particular the maximum frequency is , where f perif 56.448mhz (for STA680-51001569-05000033-c0002.000 firmware version) is the frequency of the clock feeding the peripheral bus and blocks. figure 11 shows the timing diagrams and waveform for the three spi interfaces. figure 11. spi interface timings diagrams and waveforms ta bl e 1 0 shows the timing values for the spi interface. table 10. spi interface timing values symbol parameter working rate unit min. max. tss chip select 8/fsck - ns fsck serial bit clock, slave mode 1.076 8000 khz fsck serial bit clock, master mode 1.076 25000 khz th data hold time 7 - ns ts data setup time 15 - ns f spi f perif 8 -------------- - = ac00718 d6 d5 d4 d3 d2 d1 d0 spix_sck cpol =0 ts th 1/fsck d7 z z spix_sck cpol =1 d6 d5 d4 d3 d2 d1 d0 d7 z z 1/fsck ts th tss spix_mosi/miso spix_mosi/miso spix_ss_n spix_sck cpha =0 d6 d5 d4 d3 d2 d1 d0 spix_sck cpol =0 ts th 1/fsck d7 z z spix_sck cpol =1 d6 d5 d4 d3 d2 d1 d0 d7 z z 1/fsck ts th tss spix_mosi/miso spix_mosi/miso spix_ss_n spix_sck cpha =1 free datasheet http://www.datasheet-pdf.com/
STA680 digital i/o and memory interfaces doc id 14860 rev 4 31/43 5.5.1 host micro serial peripheral interface (spi1) spi1 is used to interface the STA680 with a host processor interface. the communication with the host-microcontroller can alternatively be performed via i 2 c as described in chapter 5.6.1 . the host micro spi is a slave only interface. for the relevant pin description see ta b l e 1 1 . 5.5.2 flash serial peri pheral interface (spi2) spi2 is typically used for connecting the sta 680 to an external flash memory where the boot code and configuration parameters could be stored. the minimum required capacity for this purpose is 1 mbit. spi2 is master-only. up to 4 chip select lines are available on the STA680 with the bga package. for the relevant pin description see ta bl e 1 2 . table 11. host micro spi pin list pin name designation type drive spi1_miso host micro spi data master in/slave out o 4ma spi1_mosi host micro spi data master out/slave in i - spi1_sck host micro spi clock i 4ma spi1_ss_n host micro spi active-low slave select 1 i 4ma table 12. flash spi pin list pin name designation type drive spi2_miso flash spi data master in/slave out i - spi2_mosi flash spi data master out/slave in o 4ma spi2_sck flash spi clock o 4ma spi2_ss_n flash spi active-low slave select 1 o 4ma spi2_ss1_n flash spi active-low slave select 2 o 4ma spi2_ss2_n flash spi active-low slave select 3 (1) 1. only available in bga package. o4ma spi2_ss3_n flash spi active-low slave select 4 (1) o4ma free datasheet http://www.datasheet-pdf.com/
digital i/o and memory interfaces STA680 32/43 doc id 14860 rev 4 5.6 i 2 c interfaces the STA680 feature an i 2 c interfaces. for the relevant pin description see ta bl e 1 3 . the data pin of the i 2 c interface is an open drain driver and it needs a resistive pull- up as required by philip's iic specification. figure 12 shows timing diagrams and waveform for the two i 2 c interface. figure 12. timing diagrams and waveform for the two i 2 c interfaces in ta b l e 1 4 the timing values for the i2c interfaces are reported. table 13. host and auxiliary i 2 c interface pin list pin name designation type drive iic1_scl host micro i 2 c interface serial clock line i/o 4ma iic1_sda host micro i 2 c interface serial data line i/o 4ma iic1_da (1) 1. only available in bga package. host micro i 2 c interface data acknowledged i/o 4ma iic2_scl auxiliary i 2 c interface serial clock line i/o 4ma iic2_sda auxiliary i 2 c interface serial data line i/o 4ma iic2_da (1) auxiliary i 2 c interface data acknowledged i/o 4ma ts,dat th,dat thigh iicx_sda iicx_scl bit 1 bit 2 bit n start stop 1/fscl tlow th,sta th,sto ac00719 table 14. i 2 c interface timing values symbol parameter standard-mode fast-mode unit min. max. min. max. fscl scl clock frequency - 100 - 400 khz tlow low period of scl clock 4.7 - 1.3 - s thigh high period of scl clock 4 - 0.6 - s th, dat data hold time 5 - - s ts, dat data setup time 250 - 100 - s th, sta hold time for start condition 4 - 0.6 - s ts, sto setup time for stop condition 4 - 0.6 - s free datasheet http://www.datasheet-pdf.com/
STA680 digital i/o and memory interfaces doc id 14860 rev 4 33/43 5.6.1 host micro i 2 c interface (i2c1) i2c1 is used to connect the STA680 to the host microcontroller to transmit commands, diagnostic information, and data. the i2c1 interface is a standard bi-directional i 2 c interface. the i2c1 interface supports 7-bit addressing and 8-bit data. it can run in both standard mode (serial clock frequency up to 100 khz) and fast mode (up to 400 khz). the i 2 c device addresses are reported in ta bl e 1 5 . an additional control line called iic1_da is provided as an extension of the i 2 c standard. this line is used as a flag to show the host controller that data is available and it can be polled by the host micro in either master or slave modes. table 15. i2c1 interface device address i2c1 primary address secondary address read address 0101111b (0x2f) 0101101b (0x2d) write address 0101110b (0x2e) 0101100b (0x2c) free datasheet http://www.datasheet-pdf.com/
digital i/o and memory interfaces STA680 34/43 doc id 14860 rev 4 5.7 sdram interface the sdram interface supports up to 32m x 16 sdram; both standard and mobile protocols are accepted. for the relevant pin description see ta bl e 1 6 the minimum required sdram size for single channel application is 64 mbit while for a dual channel application at least 128 mbit are needed. figure 13 shows the timing diagrams and waveform for the sdram interface. figure 13. timing diagrams and wa veform for the sdram interface ta bl e 1 7 reports the timing values for the sdram interface table 16. sdram interface pin description pin name designation type drive sdr_d[0:15] sdram interface data bus i/o 4 ma sdr_a[0:12] sdram interface address bus o 4 ma sdr_ba[0:1] bank address o 4 ma sdr_cas_n active-low column address strobe o 8 ma sdr_ras_n active-low row address strobe o 8 ma sdr_we_n active-low write enable o 8 ma sdr_cs_n active-low chip select o 8 ma sdr_dqm0 low-byte data input/output mask o 4 ma sdr_dqm1 high-byte data input/output mask o 4 ma sdr_cke clock enable o 4 ma sdr_clk_ram3v3 clock to sdram for 3.3 v interface o 8 ma sdr_feed_clk feedback clock from sdram i 8 ma sdr_clk_ram sdr_cas sdr_a sdr_d sdr_ba sdr_we_n sdr_clk_cs sdr_ras row bank col bank din tos toh tih tis dout tcl tch tck bank bank row col cas latency = 3 write read free datasheet http://www.datasheet-pdf.com/
STA680 digital i/o and memory interfaces doc id 14860 rev 4 35/43 for power saving and reduced interference on the board, the sdram speed is programmed to work at half speed with respect to the internal data processing: full rate sw application: the sdram interface works at the same frequency as the internal data processing; half rate sw application: th e sdram interface works at half frequency with respect to the internal data processing table 17. sdram interface timing values symbol parameter condition software application min. max. unit tck scl clock period core in normal drive full rate 7.35 - ns half rate 12.05 - core in overdrive full rate 6.25 - half rate 12.05 - tch clk high level width - - 2.5 - ns tcl clk low level width - - 2.5 - ns toh data out hold time - - 0.9 - ns tos data out setup time - - 1.5 - ns tis data in setup time - - 0.8 - ns tih data in hold time - - 1.6 - ns tt transition time - - - 1.2 ns free datasheet http://www.datasheet-pdf.com/
electrical specifications STA680 36/43 doc id 14860 rev 4 6 electrical specifications 6.1 absolute maximum ratings 6.2 thermal data table 18. absolute maximum ratings symbol parameter test condition min typ max units vdd core supply voltage - - 1.47 - v vdd_gen_io generic io supply voltage --3.6-v vdd_fsh_io flash io supply voltage - - 3.6 - v vdd_ram_io sdram io supply voltage --3.6-v vdd_osc osc 1v8 supply voltage - - 1.95 - v vdd_pll_ana pll analog supply voltage - - 2.75 - v vdd_pll_dig pll digital supply voltage - - 1.47 - v vdd_saf saf core supply voltage - - 1.47 - v v i voltage on input pin - -0.5 - vddio+0. 5 v v o voltage on output pin - -0.5 - vddio+0. 5 v t stg storage temperature - -55 - 150 c t amb operative ambient temperature --40-85c v esd esd absolute minimum withstand voltage r = 1.5 k ; c = 1.5 pf human body model, bga package >|1000| v charged device mode, bga package >|500| r = 1.5 k ; c = 1.5 pf human body model, lqfp package >|1000| charged device mode, lqfp package >|450| table 19. thermal data symbol parameter lqfp lfbga unit r th j-amb thermal resistance junction-to-ambient (1) 1. according to jedec specif ication on a 4 layers board. 43 37 c/w free datasheet http://www.datasheet-pdf.com/
STA680 electrical specifications doc id 14860 rev 4 37/43 6.3 operating conditions table 20. dc electrical characteristics symbol parameter test cond ition min. typ. max. unit vdd core supply voltage normal drive 1.14 1.2 1.26 v over drive 1.33 1.4 1.47 v vdd_gen_io generic io supply voltage - 3.14 3.3 3.46 v vdd_fsh_io flash io supply voltage - 3.14 3.3 3.46 v vdd_ram_io sdram io supply voltage - 3.14 3.3 3.46 v vdd_ram_io_ 1v8 supply for the sdram clock at 1.8v - 1.71 1.8 1.89 v vdd_osc oscillator analog supply voltage - 1.71 1.8 1.89 v vdd_pll_ana pll analog supply voltage - 1.71 1.8 1.89 v vdd_pll_dig pll digital supply voltage normal drive 1.14 1.2 1.26 v over drive 1.33 1.4 1.47 v vdd_saf saf supply voltage normal drive 1.14 1.2 1.26 v over drive 1.33 1.4 1.47 v i 1v2 current from 1.2v supply (1) t amb =25c vdd=1.20v - 90 -ma t amb = 85c vdd=1.26v - - 149 ma i 3v3 current from 3.3v supply t amb =25c vdd_io (2) =3.3v - 32 -ma t amb = 85c vdd_io=3.46v - - 41 ma pd (1) power dissipation t amb =25c typical supply - 250 - mw t amb =85c max supply - - 360 mw iil low level input leakage current (3) vi = 0v - - 1.9 a iih high level input leakage current (3) vi = vdd_gen_io (4) --1.9a ilpu high level input leakage current on pull up (5) vi = vdd_gen_io (4) --2.9a ilpd low level input leakage current on pull-down (6) vi = 0v - - 10 a ipu pull-up current vi = 0v 20 - 72 a ipd pull-down current vi = vdd_gen_io (4) 20 - 72 a rpu equivalent pull-up resistance (7) vi = 0v 50 - 115 k rpd equivalent pull-down resistance (8) vi = vdd_gen_io (4) 50 - 115 k free datasheet http://www.datasheet-pdf.com/
electrical specifications STA680 38/43 doc id 14860 rev 4 vil low level input voltage 3.3 supply mode -0.3 - 0.7 v vih high level input voltage 3.3 supply mode 2.0 - vdd_g en_io +0.3 v vhyst input hysteresis voltage 3.3 supply mode 50 - - mv voh output high voltage ioh =xma (9) vdd_g en_io ? 0.4v --v vol output low voltage iol =xma (9) --0.3v ilatchup injection current maximum operating junction temperature 105 c 100 - - ma iil_ram low level input leakage current (3) vi = 0v - - 4 a iih_ram high level input leakage current (3) vi = vdd_ram_io - - 4 a ilpu_ram high level input leakage current on pull up (5) vi = vdd_ram_io - - 4 a ilpd_ram low level input leakage current on pull-down (6) vi = 0v - - - a ipu_ram pull-up current vi = 0v 44 140 a rpu_ram equivalent pull-up resistance (7) vi = 0v 25 - 87 k vil_ram low level input voltage - 0.8 - - v vih _ ram high level input voltage - - - 2 v vhyst_ ram schmitt trigger hysteresis - 300 - 800 mv voh_ ram high level output voltage ioh = -xma (9) vdd_r am_io -0.4 --v vol_ ram low level output voltage iol =xma (9) --0.3v idc 3v3 to 1v8 dc regulator output current - - - 100 ma c l output load for triple voltage pads (1.8v and 3.3v) 1.8v supply mode for 4ma buffer 40 mhz - - 30 pf 3.3v supply mode (for both 4ma and 8ma) 60 mhz - - 30 pf 75 mhz - - 20 pf table 20. dc electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
STA680 electrical specifications doc id 14860 rev 4 39/43 c l,3v3 output load for 3.3v pads 4ma buffer 140mhz - - 10 pf 8ma buffer 140mhz - - 20 pf c l, dc dc regulator output load (10) -2.2-4.7f 1. current consumption and power dissipat ion measured for single channel software a pplication running at 127mhz on core and 65mhz on sdram interface. this is the half rate commercial software release identified as STA680-51000569- 01800003-c0001.000.bin. 2. vdd_io generally refers to the supply of t he vdd_gen_io, vdd_fsh_io and vdd_ram_io groups. 3. performed on all the input pins ex cluded the pull-down and pull-up ones. 4. vdd_gen_io may be vdd_fhs_io or vd d_gen_io depending on interface considered. 5. performed only on the input pins with pull up. 6. performed only on the input pins with pull down. 7. guaranteed by ipu measurements. 8. guaranteed by ipd measurements. 9. xma = 4ma for a bd4, 8ma for bd8 pad type. 10. dielectric=x7r esrmax=100ohm, 2.2f +- 5% or any above 3f+-10% but less than 4.7f+-10%.it is also recommended to distribute the 2.2f capacitance on the board by placing equivalent number of sm aller capacitance value (for example, 470nf) near each vdd_reg1v8 supply pad. table 20. dc electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit free datasheet http://www.datasheet-pdf.com/
package information STA680 40/43 doc id 14860 rev 4 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 14. lqfp144 (20x20mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 17.500 0.6890 e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 17.500 0.6890 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0?(min.), 3.5?(typ.), 7?(max.) ccc 0.080 0.0031 lqfp144 (20x20x1.40mm) l ow profile plastic q uad f lat p ackage note 1: exact shape of each corner is optional. 0099183 c free datasheet http://www.datasheet-pdf.com/
STA680 package information doc id 14860 rev 4 41/43 figure 15. lfbga 168 balls (12x12x1.4 mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.400 0.0551 a1 0.210 0.0083 a2 0.200 0.0078 a4 0.800 0.0315 b 0.350 0.400 0.450 0.0138 0.0157 0.0177 d 11.850 12.000 12.150 0.4665 0.4724 0.4783 d1 10.400 0.4094 e 11.850 12.000 12.150 0.4665 0.4724 0.4783 e1 10.400 0.4094 e 0.800 0.0315 z 0.800 0.0315 ddd 0.100 0.0039 eee 0.150 0.0059 fff 0.080 0.0031 lfbga 168 balls l ow profile f ine pitch b all g rid a rray 8123111 b body: 12 x 12 x 1.4mm free datasheet http://www.datasheet-pdf.com/
revision history STA680 42/43 doc id 14860 rev 4 8 revision history table 21. document revision history date revision changes 25-jul-2008 1 initial release. 19-dec-2008 2 update ecopack ? information in section 7 on page 40 . 31-jul-2009 3 added section 2: hd radio? system on page 7 . changed ta b l e 2 , 4, 7, 12, 13, 13, 17 and 20. changed figure 14 , 15 , 6 , 3 , 8 and 11 . add figure 10: crystal characteristics on page 26 . 09-nov-2010 4 document status prom oted from preliminary data to datasheet. modified features . and description on page 1 . modified the flow of the sections. modified section 1: block diagram and pin description . add section 2: general description . changed figure 7: power on timing and updated ta bl e 4 : po w e r o n timing parameters . modified section 5.5: serial peripheral interfaces (spi) . updated section 6: electrical specifications . free datasheet http://www.datasheet-pdf.com/
STA680 doc id 14860 rev 4 43/43 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com free datasheet http://www.datasheet-pdf.com/

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